The present invention relates to a technique for manufacturing a semiconductor integrated circuit device and, more particularly, to a technique which is effective in achieving anticorrosion of metal wirings formed by a chemical mechanical polishing (CMP) method.
Japanese Patent Laid-open No. 135192/1995 (hereinafter referred to as xe2x80x9cHayakawaxe2x80x9d) has disclosed a post-polishing method which makes it possible to lower the particle level after polishing treatment on a wafer by performing, without drying the wafer,.a series of steps including chemical mechanical polishing, followed by wafer inverting standby, physical cleaning, chemical-cleaning (or spin-cleaning) and rinsing treatments. In the polishing apparatus to be used in this process, a wafer mounting portion in the polishing unit is made to have a construction which is capable of keeping the wafer wet, and an inter-unit wet conveying mechanism is used for conveying wafers among a polishing unit, a cleaning unit and a rinsing/drying unit, whereas an in-unit wet conveying mechanism is used for conveying wafers between the individual cleaning chambers in the cleaning unit.
A CMP apparatus for an oxide film comprising a wafer feeding portion, a polishing portion, a wafer extracting portion and a dress unit is disclosed on pp. 53 to 55 of Electronic Materials, issued in May, 1996, by the Association of Industrial Researches (hereinafter referred to as xe2x80x9cOhmura et al.xe2x80x9d). In this apparatus, the wafer is conveyed by a conveyor robot from a load cassette to a polishing portion and is polished. The polished wafer is then scrub-cleaned on its front and back sides with pure water, is stocked in an unload cassette, and thereafter, is stocked in water.
On pp. 62 to 65 of Electronic Materials, issued in May, 1996 (hereinafter referred to as xe2x80x9cTsujimura et al.xe2x80x9d), there is disclosed a technique for the transfer of a wafer in an underwater stock from a polishing step to a post-cleaning treatment (aiming at removing undesired particles such as abrasive grains introduced at the polishing time from the wafer surface and generally conducted before the wafer surface is naturally dried).
On pp. 33 to 35 of Electronic Materials, issued in May, 1996 (hereinafter referred to as xe2x80x9cHirakuraxe2x80x9d), there is disclosed a CMP apparatus comprising a polishing disc (or platen) for performing a primary polishing treatment, a polishing disc for performing a second polishing (or buff polishing) treatment, a cleaning station for cleaning the polished wafer with water and a brush, and an unloader for stocking the wafer in a submerged state.
Japanese Patent Laid-open No. 64594/1996 (hereinafter referred to as xe2x80x9cShibukixe2x80x9d) has disclosed a metal CMP process using a slurry containing an anticorrosive agent, such as BTA, so as to prevent corrosion of the metal, which might otherwise occur in the metal CMP process.
Hitherto, the metal wirings of an LSI have been formed by a process of depositing a metal film, such as an aluminum (Al) alloy film or a tungsten (W) film, over a silicon substrate (or wafer) using a sputtering method and then patterning the metal film by a dry etching method using a photoresist film as a mask.
As the integration of an LSI has become higher in recent years, however, the aforementioned process has become more critical with respect to the wiring resistance due to the finer thickness of the wiring width required by the high integration, producing a higher factor to deteriorate the performance of a logic LSI which requires an especially high performance. Therefore, recently attention has been given to wirings using copper (Cu), which has an electric resistance of about one half of that of Al alloy and an electromigration resistance higher by about one figure than that of Al alloy.
However, Cu is so low in the vapor pressure of its halide as to make it difficult to form the wirings using the dry etching treatment of the related art. Because of this difficulty, there has been introduced a wiring forming process (the so-called damascene process) by which grooves are formed in advance in the insulating film over the silicon substrate, and the Cu film is deposited over the insulating film including the insides of the grooves and any unnecessary Cu film outside the grooves is then polished back by chemical mechanical polishing (CMP) while leaving the Cu film in the grooves.
When the Cu film is polished by the CMP method, however, a portion of the Cu may be eluted by the action of an oxidizing agent added to the polishing slurry, so that a portion of the Cu wirings is corroded, thereby bringing about open defects or short-circuit defects.
This corrosion of the cu wirings characteristically occurs in the Cu wirings which are connected with the p-type diffusion layer of a pn junction (e.g., a diffusion resistance element, the source and drain of an MOS transistor, or the collector, base and emitter of a bipolar transistor) formed in the silicon substrate. Further, when the metal wirings are formed by polishing another metal material (e.g., W or an Al alloy) by the CMP method or when metal materials (or plugs) are buried in through holes for connecting upper and lower wirings, although not so serious as in the case of Cu wirings, corrosion may be caused for the aforementioned reasons if those metal wirings or plugs are connected with the pn junction.
FIG. 14(a) is a model diagram illustrating an electromotive force generating mechanism of the pn junction; FIG. 14(b) is a graph illustrating the I-V characteristics of the pn junction at a light irradiation time and at a dark time, and FIG. 15 is a model diagram illustrating a corrosion occurring mechanism of the Cu wirings.
When light comes into the pn junction formed in the silicon substrate, as shown in FIG. 14(a), an external voltage (up to 0.6 V) at + on the p-side and at xe2x88x92 on the n-side is generated by the photovoltaic effect of silicon, so that the I-V characteristics of the pn junction are shifted, as illustrated in FIG. 14(b). As a result, a short-circuit current flows, as illustrated in FIG. 15, through a closed circuit which is formed of a Cu wiring connected with the p-side (or + side) of the pn junctionxe2x80x94the pn junctionxe2x80x94the Cu wiring connected with the n-side (or xe2x88x92 side) of the pn junctionxe2x80x94the polishing slurry which has stuck to the wafer surface, so that the Cu2+ ions are dissociated from the surface of the Cu wiring connected with the p-side (or + side) of the pn junction, thereby to cause electrochemical corrosion (or electrolytic corrosion).
FIG. 16 is a graph showing relations, which occur at a time a voltage is applied, between a slurry concentration (%) and a Cu etching (eluting) rate. For a slurry concentration of 100%, as seen from FIG. 16, the eluting rate of Cu is relatively low, but abruptly rises when the polishing slurry is diluted to some extent with water. It can be said from the foregoing discussion that, when light comes in a pn junction in a case where some of the polishing slurry or its aqueous solution has stuck to the surface of the silicon wafer, the elution of Cu grows prominent to cause electrolytic corrosion. Concretely, when light comes in the surface of the wafer either in the course of conveyance from the polishing step to the post-cleaning step or at a standby time, electrolytic corrosion occurs in the Cu wirings connected with the p-type diffusion layer of the pn junction.
An object of the present invention is to provide a technique which is capable of preventing the corrosion of metal wirings formed by using the CMP method.
This and other objects and various novel features of the invention will become apparent from the following description when taken in conjunction with the accompanying drawings.
A representative aspect of the invention to be disclosed herein will be briefly described in the following.
A process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming metal wirings by forming a metal layer (or conductive layer) over the major face of a wafer and then by planarizing the metal layer by a chemical mechanical polishing (CMP) method. The so-called xe2x80x9cCMP techniquexe2x80x9d for planarizing the metal layer includes one technique using a standard polishing pad and floating abrasive grains, one technique using stationary abrasive grains, an intermediate technique and the so-called xe2x80x9cabrasion grain free CMPxe2x80x9d technique using a slurry containing substantially no abrasive grains. Further, the planarizing treatment includes not only a wiring burying technique, such as used in the damascene or dual damascene processes, but also the metal CMP technique for burying metal plugs. The method further includes the steps of forming a hydrophobic protective film over the surface of the metal wirings by pre-cleaning the planarized major face of the wafer just after the polishing treatment with a view to clearing the wafer surface of an undesired chemical, such as the oxidizing agent at the polishing time, and by anticorroding the pre-cleaned major face. The anticorroding treatment may be the cleaning step itself or its sub-step having a main object to form a hydrophobic protective film over the surface of the metal. Just after this, the anticorroding treatment is performed simultaneously with the cleaning treatment. The xe2x80x9cjust afterxe2x80x9d indicator means xe2x80x9cbefore the wafer surface is dried after the polishing treatmentxe2x80x9d or xe2x80x9cbefore the metal is corroded with a residual oxidizing agentxe2x80x9d. By this anticorroding treatment, it is possible to prevent the electrochemical corrosion of the metal wirings to a considerable extent. The term xe2x80x9celectrochemical corrosionxe2x80x9d refers to the corrosion of the metal accompanied by the battery action of the formed closed circuit which includes the metal, the pn junction, the metal and the polishing liquid component on the pattern of the wafer. The method further comprises the steps of immersing the anticorroded major face of the wafer or keeping it in a wet state so that it may not become dry. The term xe2x80x9cwet stockxe2x80x9d generally means xe2x80x9ckeeping or transfersxe2x80x9d while preventing a dry state by immersing the wafer in pure water or the like, by feeding a pure water shower or by keeping the wafer in a saturated vapor atmosphere. The method then provides the step of post-cleaning the major face of the wafer which has been kept in the wet state. The xe2x80x9cpost-cleaningxe2x80x9d treatment is generally performed before the surface becomes dry, with a view to clearing the wafer surface of undesired particles, such as abrasive grains introduced at the polishing time. This cleaning treatment frequently involves both a mechanical cleaning treatment, such as a scrub cleaning treatment using a brush, and a weak etching treatment with a chemical solution.
A summary of the features of the invention will be briefly described as follows.
1. A process for manufacturing a semiconductor integrated circuit device, comprising the steps of:
(a) forming a metal layer whose main component is a metal, over a first major face of a wafer having a pattern of a semiconductor integrated circuit;
(b) planarizing the first major face, having the formed metal layer, of the wafer by a chemical mechanical polishing method;
(c) anticorroding the planarized first major face of the wafer;
(d) immersing the anticorroded first major face of the wafer in a liquid or keeping the same in a wet state so that it may not become dry; and
(e) post-cleaning the first major face, kept in the wet state, of the wafer.
2. A process for manufacturing a semiconductor integrated circuit device according to Item 1, wherein the anticorroding step (c) includes the steps of: mechanically cleaning a polishing slurry which has stuck to the first major face at the step (b); and forming a protective film over the surface portion of the metal layer of the first major face, from which the polishing slurry has been removed, of the wafer.
3. A process for manufacturing a semiconductor integrated circuit device according to Item 2, wherein the protective film is a hydrophobic protective film.
4. A process for manufacturing a semiconductor integrated circuit device according to any one of Items 1 to 3, wherein the post-cleaning step (e) includes the step of mechanically cleaning the foreign particles which have stuck to the first major face of the wafer at the step (b).
5. A process for manufacturing a semiconductor integrated circuit device, comprising the steps of: (a) forming a metal layer whose main component is copper, over a first major face of a wafer having a pattern of a semiconductor integrated circuit;
(b) planarizing the first major face, having the formed metal layer, of the wafer by a chemical mechanical polishing method;
(c) anticorroding the planarized first major face of the wafer;
(d) immersing the anticorroded first major face of the wafer in a liquid or keeping the same in a wet state so that it may not become dry; and
(e) post-cleaning the first major face, kept in the wet state, of the wafer.
6. A process for manufacturing a semiconductor integrated circuit device, comprising the steps of:
(a) forming a metal layer whose main component is a metal, over a first major face of a wafer having a pattern of a semiconductor integrated circuit;
(b) planarizing the first major face, having the formed metal layer, of the wafer by a chemical mechanical polishing method;
(c) anticorroding the planarized first major face of the wafer; and
(d) immersing the anticorroded first major face of the wafer in a liquid or keeping the same in a wet state at a shaded wafer stocking portion so that it may not become dry.
7. A process for manufacturing a semiconductor integrated circuit device according to Item 6, wherein the wafer stocking portion is shaded to have an illuminance of 500 luxes or less.
8. A process for manufacturing a semiconductor integrated circuit device according to Item 6, wherein the wafer stocking portion is shaded to have an illuminance of 300 luxes or less.
9. A process for manufacturing a semiconductor integrated circuit device, comprising the step of:
(a) forming a metal layer whose main component is a metal, over a first major face of a wafer having a pattern of a semiconductor integrated circuit;
(b) planarizing the first major face, having the formed metal layer, of the wafer by a chemical mechanical polishing method; and
(c) drying the planarized first major face of the wafer just after the planarizing step.
10. A process for manufacturing a semiconductor integrated circuit device, comprising the steps of:
(a) forming a metal layer whose main component is a metal, over a first major face of a wafer having a pattern of a semiconductor integrated circuit;
(b) planarizing the first major face, having the formed metal layer, of the wafer by a chemical mechanical polishing method; and
(c) post-cleaning the planarized first major face of the wafer at a shaded post-cleaning portion.
11. A process for manufacturing a semiconductor integrated circuit device according to Item 10, wherein the post-cleaning step (c) includes the step of removing a foreign particle by applying a mechanical friction to the first major face of the wafer in the presence of an alkaline or weakly alkaline chemical.
12. A process for manufacturing a semiconductor integrated circuit device, comprising the steps of:
(a) forming a metal layer whose main component is a metal, over a first major face of a wafer having a pattern of a semiconductor integrated circuit;
(b) planarizing the first major face, having the formed metal layer, of the wafer by a chemical mechanical polishing method;
(c) anticorroding the planarized first major face of the wafer; and
(d) post-cleaning the anticorroded first major face of the wafer.
13. A process for manufacturing a semiconductor integrated circuit device, comprising the steps of:
(a) forming a metal layer whose main component is copper, over a first major face of a wafer having a pattern of a semiconductor integrated circuit;
(b) planarizing the first major face, having the formed metal layer, of the wafer by a chemical mechanical polishing method; and
(c) forming a hydrophobic protective film over the planarized surface of the metal layer by anticorroding the planarized first major face of the wafer.
14. A process for manufacturing a semiconductor integrated circuit device, comprising the steps of:
(a) forming a metal layer whose main component is a metal, over a first major face of a wafer having a pattern of a semiconductor integrated circuit;
(b) planarizing the first major face, having the formed metal layer, of the wafer by a chemical mechanical polishing method using a sheet treatment; and
(c) post-cleaning the planarized first major face of the wafer at a shaded post-cleaning portion.
15. A process for manufacturing a semiconductor integrated circuit device, comprising the steps of:
(a) forming a metal layer whose main component is a metal, over a first major face of a wafer having a pattern of a semiconductor integrated circuit;
(b) planarizing the first major face, having the formed metal layer, of the wafer by a chemical mechanical polishing method using a sheet treatment;
(c) anticorroding the planarized first major face of the wafer; and
(d) post-cleaning the anticorroded first major face of the wafer.
16. A process for manufacturing a semiconductor integrated circuit device, comprising the steps of:
(a) forming a metal layer whose main component is a metal, over a first major face of a wafer having a pattern of a semiconductor integrated circuit;
(b) planarizing the first major face, having the formed metal layer, of the wafer by a chemical mechanical polishing method;
(c) anticorroding the planarized first major face of the wafer; and
(d) immersing the anticorroded first major face of the wafer in a liquid or keeping the same in a wet state at a shaded wafer stocking portion, kept at a temperature as low as not to proceed an electrochemical corrosion substantially, so that it may not become dry.
17. A process for manufacturing a semiconductor integrated circuit device, comprising the steps of:
(a) forming a metal layer whose main component is a metal, over a first major face of a wafer having a pattern of a semiconductor integrated circuit;
(b) planarizing the first major face, having the formed metal layer, of the wafer by a chemical mechanical polishing method; and
(c) forming a protective film over the planarized surface of the metal layer by anticorroding the planarized first major face of the wafer.
18. A process for manufacturing a semiconductor integrated circuit device according to Item 17, the anticorroding step
(c) is conducted under such a condition that an oxidizing agent having stuck to the first major face of the wafer at the step (b) does not substantially act.
19. A process for manufacturing a semiconductor integrated circuit device according to Item 17 or 18, wherein the protective film is a hydrophobic protective film.
20. A process for manufacturing a semiconductor integrated circuit device, comprising the steps of:
(a) forming a metal layer whose main component is a metal, over a first major face of a wafer having a pattern of a semiconductor integrated circuit;
(b) planarizing the first major face, having the formed metal layer, of the wafer by a chemical mechanical polishing method using a sheet treatment;
(c) anticorroding the planarized first major face of the wafer;
(d) immersing the anticorroded first major face of the wafer in a liquid or keeping the same in a wet state so that it may not become dry; and
(e) post-cleaning the first major face, kept in the wet state, of the wafer.
The summary of other invention will be briefly described by itemizing it, as follows.
21. A process for manufacturing a semiconductor integrated circuit device, comprising the steps of:
(a) forming a plurality of semiconductor elements over the major face of a semiconductor substrate;
(b) forming a metal layer over the plurality of semiconductor elements through an insulating film;
(c) forming a plurality of metal wirings, electrically connected with the plurality of semiconductor elements, by planarizing the metal layer by a chemical mechanical polishing method;
(d) anticorroding the surfaces of the metal wirings;
(e) immersing the anticorroded surfaces of the metal wirings in a liquid or keeping the same in a wet state so that they may not become dry; and
(f) post-cleaning the surfaces, kept in the wet state, of the metal wirings.
22. A process for manufacturing a semiconductor integrated circuit device according to Item 21, wherein the anticorroding step (d) includes the steps of: removing a polishing slurry, having stuck to the surfaces of the metal wirings, by a mechanism cleaning treatment; and forming a protective film over the surfaces, from which the polishing slurry was removed, of the metal wirings.
23. A process for manufacturing a semiconductor integrated circuit device according to Item 22, wherein the protective film is a hydrophobia protective film.
24. A process for manufacturing a semiconductor integrated circuit device according to any one of Items 21 and 23, wherein the plurality of semiconductor elements have a pn junction, and the plurality of metal wirings are partially electrically connected with one of the pn junction whereas the remaining plurality of metal wirings are electrically connected with the other of the pn junction.
25. A process for manufacturing a semiconductor integrated circuit device according to any one of Items 21 to 24, wherein the metal wirings include metal plugs.
26. A process for manufacturing a semiconductor integrated circuit device according to any one of Items 21 to 25, wherein the metal wirings contain at least copper.
27. A process for manufacturing a semiconductor integrated circuit device according to any one of Items 21 to 26, wherein the anticorroded surfaces of the metal wirings are dipped in a liquid or kept in a wet state at a shaded wafer stocking portion, so that they may not become dry.
28. A process for manufacturing a semiconductor integrated circuit device according to Item 27, wherein the wafer stocking portion is shaded to have an illuminance of 500 luxes or less.
29. A process for manufacturing a semiconductor integrated circuit device according to Item 27, wherein the wafer stocking portion is shaded to have an illuminance of 300 luxes or less.
30. A process for manufacturing a semiconductor integrated circuit device according to Item 27, wherein the wafer stocking portion is shaded to have an illuminance of 100 luxes or less.
31. A process for manufacturing a semiconductor integrated circuit device, comprising the steps of:
(a) forming a plurality of semiconductor elements over the major face of a semiconductor substrate;
(b) forming a metal layer over the plurality of semiconductor elements through an insulating film;
(c) forming a plurality of metal wirings, electrically connected with the plurality of semiconductor elements, by planarizing the metal layer by a chemical mechanical polishing method; and
(d) post-cleaning the planarized surfaces of the metal wirings, after shaded, at a post-cleaning portion.
32. A process for manufacturing a semiconductor integrated circuit device according to Item 31, wherein the metal wirings contain at least copper.
33. A process for manufacturing a semiconductor integrated circuit device comprising the steps of:
(a) forming a plurality of semiconductor elements over the major face of a semiconductor substrate;
(b) forming a metal layer over the plurality of semiconductor elements through an insulating film;
(c) forming a plurality of metal wirings, electrically connected with the plurality of semiconductor elements, by planarizing the metal layer by a chemical mechanical polishing method; and
(d) drying the planarized surfaces of the metal wirings just after the planarizing treatment.
34. A process for manufacturing a semiconductor integrated circuit device according to Item 33, wherein the metal wirings contain at least copper.